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19-4774; Rev 1; 4/99
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs
General Description
The MAX3690 serializer is ideal for converting 8-bitwide, 77Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts TTL clock and data inputs, and delivers a 3.3V differential PECL serialdata output. A fully integrated PLL synthesizes an internal 622MHz serial clock from a low-speed crystal reference clock (77.76MHz, 51.84MHz, or 38.88MHz). The MAX3690 is available in the extended-industrial temperature range (-40C to +85C) in a 32-pin TQFP package.
____________________________Features
o Selectable Reference Clock Frequency: 77.76MHz, 51.84MHz, or 38.88MHz o Single +3.3V Supply o 77Mbps (8-bit) Parallel to 622Mbps Serial Conversion o Clock Synthesis for 622Mbps Serial Data o 200mW Power o TTL Parallel Clock and Data Inputs o Differential 3.3V PECL Serial-Data Output
MAX3690
________________________Applications
622Mbps SDH/SONET Transmission Systems 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross Connects
PART MAX3690ECJ
Ordering Information
TEMP. RANGE -40C to +85C PIN-PACKAGE 32 TQFP
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
38.88MHz TTL CRYSTAL REFERENCE VCC = +3.3V
PCLKI PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PCLKO
RCLK
VCC
CKSET
1F
1F
OVERHEAD GENERATION
MAX3690
FIL+ FIL-
GND
SD-
SD+ VCC = +3.3V 130 130
VCC = +3.3V
MAX3668
82 THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50).
82
________________________________________________________________ Maxim Integrated Products
1
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+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs MAX3690
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC .......................................................................-0.5V to +5V All Inputs, FIL-, FIL+, PCLKO .................-0.5V to (VCC + 0.5V) Output Current PECL Outputs (SD).......................................................50mA Continuous Power Dissipation (TA = +85C) TQFP (derate 10.2mW/C above +85C) .....................663mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-60C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50 1% to (VCC - 2V), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current CKSET Input Current PECL OUTPUTS (SD) Output High Voltage Output Low Voltage VOH VOL TA = 0C to +85C TA = -40C TA = 0C to +85C TA = -40C VCC - 1.025 VCC - 1.085 VCC - 1.81 VCC - 1.83 2.0 0.8 VIN = VCC VIN = 0 IOH = 400A IOL = -400A -10 -10 2.4 0.44 10 10 VCC - 0.88 VCC - 0.88 VCC - 1.62 VCC - 1.555 V V SYMBOL ICC ICKSET CONDITIONS PECL outputs unterminated CKSET = 0 or VCC MIN TYP 60 MAX 100 500 UNITS mA A
TTL INPUTS AND OUTPUTS (PCLKI, RCLK, PCLKO, PD_) Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage VIH VIL IIH IIL VOH VOL V V A A V V
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50 1% to (VCC - 2V), all TTL thresholds set to VCC/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER Serial Clock Rate Parallel Data Setup Time Parallel Data Hold Time Allowable Parallel Clock Output to Parallel Clock Input Delay Output Random Jitter PECL Differential Output Rise/Fall Time TTL Output Rise Time TTL Output Fall Time SYMBOL fSCLK tSU tH tSKEW 0 tR, tF tR tF 20% to 80% CLOAD = 15pF, VOUT = 0.8V to 2.0V CLOAD = 15pF, VOUT = 0.8V to 2.0V 200 650 550 1200 1000 0 5.0 11 CONDITIONS MIN TYP 622.08 MAX UNITS MHz ps ps ns psRMS ps ns ns
Note 1: AC characteristics guaranteed by design and characterization. Note 2: All TTL thresholds set to VCC / 2. 2 _______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs
__________________________________________Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
MAX3690
SUPPLY CURRENT vs. TEMPERATURE
MAX3690-01
PARALLEL DATA SETUP TIME vs. TEMPERATURE
MAX3690-02
PARALLEL DATA HOLD TIME vs. TEMPERATURE
265 260 255 250 245 240 235 230
MAX3690-03
75 70 SUPPLY CURRENT (mA) 65 60 55 50 45 -50 -25 0 25 50 75
-55 PARALLEL DATA SETUP TIME (ps) -60 -65 -70 -75 -80 -85 -90 -95
270 PARALLEL DATA HOLD TIME (ps)
100
-40 -25
0
25
50
75
85
-40
-25
0
25
50
75
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
SERIAL DATA RANDOM JITTER (RCLKI = 77.76MHz)
MAX3690-05
ALLOWED PCLKO to PCLKI SKEW vs. TEMPERATURE
MAX3690-07
SERIAL-DATA OUTPUT EYE DIAGRAM (622Mbps, PRBS)
MAX3690-08
VCC = 3.3V
15
10 TIME (ns) 2mV/ div 100mV/ div 5
0 RJ = 4.66psRMS 5ps/div TEMPERATURE (C) -5 0 -50 0 TEMPERATURE (C) 50 100 200ps/div
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs MAX3690
______________________________________________________________Pin Description
PIN 1-8 9, 10, 17, 18, 19, 24, 25, 26, 31, 32 11 12, 13, 16, 21, 28, 29 14 15 NAME PD0-PD7 FUNCTION TTL Parallel-Data Inputs. Data is clocked in on the PCLKI signal's positive transition.
GND
Ground
PCLKO VCC SDSD+
TTL Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. +3.3V Supply Voltage Inverting PECL Serial-Data Output Noninverting PECL Serial-Data Output Reference Clock Rate Programming Pin. CKSET = open: Reference clock rate = 77.76MHz CKSET = 20k to GND: Reference clock rate = 51.84MHz CKSET = GND: Reference clock rate = 38.88MHz Filter Capacitor Input. Connect a 1F capacitor between FIL- and VCC. Filter Capacitor Input. Connect a 1F capacitor between FIL- and VCC. TTL Reference-Clock Input. Connect a crystal reference clock (77.76MHz, 51.84MHz or 38.88MHz) to the RCLK input. The active edge is the positive transitioning edge. TTL Parallel-Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI input. The active edge is the positive transitioning edge.
20
CKSET
22 23 27 30
FILFIL+ RCLK PCLKI
_______________Detailed Description
The MAX3690 serializer comprises an 8-bit parallel input register, an 8-bit shift register, control and timing logic, a PECL output buffer, TTL input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/frequency detector, loop filter/amplifier, voltagecontrolled oscillator, and programmable prescaler). This device converts 8-bit-wide, 77Mbps parallel data to 622Mbps serial data (Figure 1). The PLL synthesizes an internal 622MHz reference used to clock the output shift register. This clock is generated by locking onto the external crystal reference clock signal (RCLK) operating at either 77.76MHz, 51.84MHz, or 38.88MHz. The incoming par-
allel data is clocked into the MAX3690 on the rising transition of the parallel-clock-input signal (PCLKI). The control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (PCLKO). PCLKO is the synthesized 622MHz internal serial-clock signal divided by eight. Parallelclock output to parallel-clock-input delay (skew) must be observed. Figure 2 shows the timing diagram.
PECL Outputs
The serial-data PECL outputs (SD+, SD-) require 50 DC termination to (VCC - 2V). See the Alternative PECLOutput Termination section.
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_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs MAX3690
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 TTL TTL TTL TTL TTL TTL TTL 8-BIT PARALLEL INPUT REGISTER TTL
PCLKI CKSET
TTL
PRESCALER
SHIFT 8-BIT SHIFT REGISTER PECL SDOH SDOL
RCLK
TTL
PHASE/FREQ DETECT
VCO
CONTROL
LATCH
TTL
MAX3690
FIL+ FILPCLKO
Figure 1. Functional Diagram
PCLKO tSKEW
PCLKI tSU PD_ VALID PARALLEL DATA tH
SD
D7
D6
D5
D4
D3
D2
D1
D0
NOTE: PD7 = D7, PD6 = D6, PD5 = D5, PD4 = D4, PD3 = D3, PD2 = D2, PD1 = D1, PD0 = D0
Figure 2. Timing Diagram
_______________________________________________________________________________________ 5
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs MAX3690
__________Applications Information
Alternative PECL-Output Termination
Figure 3 shows alternative PECL-output-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, be sure that the coupling capacitor is placed following the 50 or Theveninequivalent DC termination.
130 130 +3.3V
MAX3690
SD+ Z0 = 50 PECL INPUTS
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3690 data outputs.
MAX3690
SD-
Z0 = 50 82 82
SD+
Z0 = 50
HIGHIMPEDENCE INPUTS
SD-
Z0 = 50
50 VCC - 2V
50
Figure 3. Alternative PECL-Output Termination
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_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs
Pin Configuration
GND FIL+ FILVCC CKSET GND GND GND
MAX3690
TOP VIEW
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
GND GND RCLK VCC VCC PCLKI GND GND
25 26 27 28 29 30 31 32
MAX3690
VCC SD+ SDVCC VCC PCLKO GND GND
_______________________________________________________________________________________
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
1 2 3 4 5 6 7 8
TQFP
7
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs MAX3690
Package Information
TQFPPO.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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